1. Field of the Invention
The present invention generally relates to a test fixture for supporting a semiconductor device package while its semiconductor chip is being tested. More particularly, the present invention relates to a test fixture for electrically connecting a semiconductor chip of a semiconductor device package to a test board, and which fixture allows the backside of the chip to be analyzed while signals are supplied to the chip via the test board. The present invention also relates to a testing module comprising a decapsulated semiconductor device package mounted to a test fixture.
2. Description of the Related Art
Testing the quality of semiconductor integrated circuits usually includes a hot spot detection test. Hot spot detection tests can be carried out using any one of three techniques: Emission Microscopy (EMS), Liquid Crystal, and Optical Beam Induced Current (OBIC) techniques. Emission Microscopy is a technique of collecting photons from a semiconductor chip after providing a power supply voltage to the semiconductor chip. The collected photons are analyzed to uncover any defective component of the chip. Specifically, an emission microscope has a detector which detects infrared light emitted from the chip.
In some devices having a relatively complex circuit layout, an area of potential failure of the chip is located at the front of the chip but under the power bus lines. In a multi-layer metal device, an area of potential failure is also located nearest to the front of the chip but under multiple layers of metal lines. In a specialty package known as a flip chip, the front of the chip is in effect flipped over and thus cannot be exposed. Accordingly, the front of such chips cannot be analyzed for defects using a conventional hot spot detection technique.
Recently, LOC (Lead-On-Chip) packages have been widely used in memory devices. However, the active front surface of the chip of a LOC is blocked by the leads of a lead frame of the package. Accordingly, these packages also can not be analyzed for failures from the front of the chip.
Therefore, tests from the back of a chip have been developed to detect the location and cause of semiconductor package device failures. Such backside failure analysis is disclosed in T. Ishii and K. Miyamoto, xe2x80x9cFunctional Failure Analysis Technology from Backside of VLSI Chipxe2x80x9d, Proceedings of the 20th International Symposium for Testing and Failure Analysis (ISFTA), 1994, pp. 41xcx9c47; N. M. Wu et. al., xe2x80x9cFailure Analysis from Back Side of Diexe2x80x9d, ISTFA, 1996, pp. 393xcx9c399; and Jeong-Seon Seo et. al, xe2x80x9cIntelligent Defect Localization Methodology Through the Use of Photoemission Spectral Analysisxe2x80x9d, ISTFA, 1995, pp. 22xcx9c27.
The first important step in conducting backside analysis is backside decapsulation. For a flip chip, backside decapsulation is not problematic. However, for a regularly packaged chip, backside decapsulation is relatively difficult because the die pad and the adhesive attaching the chip to the die pad need to be removed. In addition, the back of the chip needs to be ground and polished to make the chip thinner.
The backside decapsulation process may be summarized as follows. First, a portion of the package is removed so that the die pad is exposed. The die pad is removed, and then the adhesive attached to the back of the chip is washed away with acetone. Then, the back of the chip is ground to make the chip thinner, and is polished to remove scratches having a size of at least 1 xcexcm. After that, the back of the chip is washed and cleaned.
A wet-etching method using an etchant such as N2 or H2SO4, or a drill or a milling machine may be used to decapsulate the back of the package. The backside decapsulation process involving the use of a drill or milling machine is carried out as follows. First, the back of the package is ground away by a milling machine or a hand drill until the die pad is exposed. The area removed from the back of the package thus needs to be as large as that of the die pad. A metal such as silver (Ag), which is attached between the die pad and the back of the semiconductor chip for improving the electrical conductivity, is removed by a blade or by tweezers. The adhesive attaching the semiconductor chip to the die pad is then easily removed with a cotton-tipped swab saturated with acetone. After that, the back of the semiconductor chip is ground by a diamond-headed tip to reduce the thickness of the chip.
To conduct a backside failure analysis using the hot spot detection technique, the decapsulated semiconductor device package must be mounted on a test board, which is connected to a test apparatus. The test board has wiring patterns, which are electrically connected to the outer leads of the semiconductor device package. However, if a semiconductor device package having a decapsulated backside is mounted on a test board with the back of the package facing the wiring patterns at the upper surface of the test board, the decapsulated backside of the semiconductor device package would not be exposed in a manner which would allow for a backside failure analysis to be performed.
Therefore, an object of the present invention is to provide a test fixture which will support a semiconductor device package having a decapsulated backside in a manner which allows a backside failure analysis of the semiconductor chip of the package to be performed.
Another object of the present invention is to provide a testing module which, when connected to a test board, allows a decapsulated semiconductor device package thereof to undergo backside failure analysis while power is supplied via the test board to a chip of the package.
In the testing module of the present invention, the semiconductor device package includes a semiconductor chip having an active front at which integrated circuits are formed, a back, a package body, and a plurality of leads for electrically connecting the semiconductor chip to an external apparatus. The package body of the semiconductor device package has a backside, which is partially decapsulated so as to expose the back of the semiconductor chip, and a front which is opposed to the back side.
The test fixture of the present invention includes a fixture body, a cover, and a plurality of connection pins. The fixture body has a loading surface which contacts the front of the package body and supports the package. The cover has an opening for exposing the back of the semiconductor chip, and a plurality of projections for contacting the leads of the semiconductor device package. The connection pins have inner ends which are electrically connected to the leads of the semiconductor device package, and outer ends integral with the inner ends. The outer ends of the connection pins protrude from the fixture body and are electrically connected to external apparatus.
Further, the inner ends of the connection pins comprise buffer parts. The buffer parts prevent the leads of the semiconductor device package from being damaged, and reduce the contact resistance between the leads and the connection pins.
The projections of the cover and the inner ends of the connection pins may be configured appropriately for the test fixture of the present invention to be suitable for use with various types of packages, such as SOJs (Small Outline J-leaded), QFPs (Quad Flat Package), SOPs (Small Outline Package), PLCCs (Plastic Leaded Chip Carrier), and DIPs (Dual Inline Package).